Are you an innovative engineer ready to tackle exciting challenges? Whether you specialize in mechanical, electrical, aerospace, or any other field of engineering, TeamGlobal has opportunities that will align with your career goals. We are now actively seeking an FPGA/ASIC Design Engineer for an engaging opportunity in Camden, NJ. Want to learn more? Reach out to one of our dedicated Recruiters, who will share the exciting details about this position and our impressive benefits, including the $10K in free life insurance! Join us at TeamGlobal—where excellence empowers us! Let’s connect and take your career to new heights!
Role SummaryThe FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for the delivery of complex FPGAs AND/OR ASICs systems. This is a key, high-impact, high-visibility role in the organization to ensure robust quality and delivery of Communication products for National Security. Education and Job Requirements
* A minimum of 3 years of experience with a proven track record of implementing complex algorithms targeting ASIC/FPGAs.
* A Bachelor of Science in Electrical Engineering or Computer Science or equivalent, Master of Science in
* Electrical Engineering or Computer Science preferred.
* Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado.
* Possess excellent Analytical/Debugging skills.
* Possess good verbal, written, and presentation skills.
* US Citizenship required. Preferred Skills
* A high-level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP), and System Verilog Assertions (SVA).
* Possess knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
* Working with the Ethernet protocol (not just instantiating the IP) is a big plus.
* Mentor EDA CDC/Lint/AC/RDC is a big plus.
* High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP), and System Verilog Assertions (SVA).
* Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) Job Duties/Functions
* Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex, Xilinx MPSOC) AND/OR ASICs.
* Additionally, will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
* L3T has deployed state-of-the-art EDA flows/methodologies, including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA, including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), and Catapult (HLS).
